DS449 Datasheet, PDF (7/9 Pages) Xilinx, Inc – LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)

LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)
Bus Usage
FSL Peripheral Interconnect Mechanism
FSL peripherals can be created as a master or a slave to the FSL bus.
A peripheral connected to the master ports of the FSL bus pushes data and control signals onto the FSL. All
peripherals that act as a master to the FSL bus should create a bus interface of the type MASTER for the bus
standard FSL in the Microprocessor Peripheral Description (MPD) file. Further, the peripheral must form default
connections to all master ports of the FSL bus and must follow the FSL bus write operation timing requirements as
specified in Figure 2.
A peripheral connected to the slave ports of the FSL bus reads and pops data and control signals from the FSL. All
peripherals that are a slave to the FSL bus should create a bus interface of the type SLAVE for the bus standard FSL
in the MPD file. Further, the peripheral must form default connections to all slave port of the FSL bus and must
follow the FSL bus read operation timing requirements as shown in Figure 3.
An example MPD of a simple peripheral having a master interface FSL_OUT and a slave interface FSL_IN follows.
BEGIN my_fsl_peripheral
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
BUS_INTERFACE BUS = FSL_IN, BUS_STD = FSL, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = FSL_OUT, BUS_STD = FSL, BUS_TYPE = MASTER
## Ports
PORT CLK = "", DIR = IN, SIGIS=CLK
PORT RESET = "", DIR = IN
PORT FSL_S_READ = FSL_S_Read, DIR=out, BUS=FSL_IN
PORT FSL_S_DATA = FSL_S_Data, DIR=in, VEC=[0:31], BUS=FSL_IN
PORT FSL_S_CONTROL = FSL_S_Control, DIR=in, BUS=FSL_IN
PORT FSL_S_EXISTS = FSL_S_Exists, DIR=in, BUS=FSL_IN
PORT FSL_M_WRITE = FSL_M_Write, DIR=out, BUS=FSL_OUT
PORT FSL_M_DATA = FSL_M_Data, DIR=out, VEC=[0:31], BUS=FSL_OUT
PORT FSL_M_CONTROL = FSL_M_Control, DIR=out, BUS=FSL_OUT
PORT FSL_M_FULL = FSL_M_Full, DIR=in, BUS=FSL_OUT
END
MicroBlaze Soft Processor FSL Interfaces
The put and get instructions of the MicroBlaze processor can be used to transfer the contents of a MicroBlaze
processor register onto the FSL bus and vice-versa. The FSL bus configuration of the MicroBlaze processor can be
used in conjunction with any of the other bus configurations. See the MicroBlaze Processor Reference Guide [Ref 1]
for more information about using FSL from the MicroBlaze processor.
Design Implementation
Design Tools
The FSL V20 design is implemented in VHDL. XST is the synthesis tool used for synthesizing the FSL V20 design.
The NGC netlist output generated by XST is then input to the Xilinx ISE tool suite for FPGA implementation.
DS449 December 18, 2012
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Product Specification