XQ18V04_03 Datasheet, PDF (8/15 Pages) Xilinx, Inc – IEEE Std 1149.1 boundary-scan (JTAG) support

QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
R
Table 6 lists the IDCODE register values for the XQ18V00
devices.
Table 6: IDCODEs Assigned to XQ18V04 Devices
ISP PROM
IDCODE
XQ18V04
05036093h
XQ18V04 TAP Characteristics
The XQ18V04 device performs both in-system program-
ming and IEEE 1149.1 boundary-scan (JTAG) testing via a
single 4-wire Test Access Port (TAP). This simplifies system
designs and allows standard Automatic Test Equipment to
perform both functions. The AC characteristics of the
XQ18V04 TAP are described as follows.
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply informa-
tion about the device’s programmed contents. By using the
USERCODE instruction, a user-programmable identifica-
tion code can be shifted out for examination. This code is
loaded into the USERCODE register during programming of
the XQ18V04 device. If the device is blank or was not
loaded during programming, the USERCODE register will
contain FFFFFFFFh.
TAP Timing
Figure 7 shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
TCK
TMS
TDI
TDO
T_CKMIN
T_MSS
T_DIS
T_MSH
T_DIH
T_DOV
Figure 7: Test Access Port Timing
TAP AC Parameters
Table 7 shows the timing parameters for the TAP waveforms
shown in Figure 7.
Table 7: Test Access Port Timing Parameters
Symbol
Parameter
T_CKMIN
T_MSS
T_MSH
T_DIS
T_DIH
T_DOV
TCK minimum clock period
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO valid delay
Min
Max
200
-
10
-
25
-
10
-
25
-
-
25
DS026_04_020300
Units
ns
ns
ns
ns
ns
ns
8
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DS125 (v1.0) December 16, 2003
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