XQ18V04_03 Datasheet, PDF (6/15 Pages) Xilinx, Inc – IEEE Std 1149.1 boundary-scan (JTAG) support

QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
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In-System Programming
In-System Programmable PROMs can be programmed indi-
vidually, or two or more can be chained together and pro-
grammed in-system via the standard 4-pin JTAG protocol as
shown in Figure 5. In-system programming offers quick and
efficient design iterations and eliminates unnecessary pack-
age handling or socketing of devices. The Xilinx develop-
ment system provides the programming data sequence
using either Xilinx iMPACT software and a download cable,
a third-party JTAG development system, a JTAG-compatible
board tester, or a simple microprocessor interface that emu-
lates the JTAG instruction sequence. The iMPACT software
also outputs serial vector format (SVF) files for use with any
tools that accept SVF format and with automatic test equip-
ment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
OE/RESET
The ISP programming algorithm requires issuance of a
reset that will cause OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130, the Xilinx MultiPRO, or a third party
device programmer. This provides the added flexibility of
using pre-programmed devices in board design and
boundary-scan manufacturing tools, with an in-system pro-
grammable option for future enhancements and design
changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 2,000 in-system program/erase
cycles and a minimum data retention of ten years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorpo-
rate advanced data security features to fully protect the pro-
gramming data against unauthorized reading. Table 4
shows the security setting available.
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 4: Data Security Options
Default = Reset
Set
Read Allowed
Program/Erase Allowed
Verify Allowed
Read Inhibited via JTAG
Program/Erase Allowed
Verify Inhibited
V CC
GND
(a)
(b)
DS026_02_011100
Figure 5: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
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DS125 (v1.0) December 16, 2003
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