XQ18V04_03 Datasheet, PDF (11/15 Pages) Xilinx, Inc – IEEE Std 1149.1 boundary-scan (JTAG) support

R
QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
.AC Characteristics Over Operating Conditions for XQ18V04
CE
OE/RESET
CLK
DATA
TSCE
THCE
TLC
THC
TCYC
THOE
TOE
TCE
TCAC
TOH
TDF
TOH
Figure 8: Pin-to-Pin Timing Diagram
DS026_06_012000
Table 12: AC Timing Characteristics for Single Device
Symbol
Description
Min
Max
T_OE
OE/RESET to data delay
-
10
T_CE
CE to data delay
-
20
T_CAC
CLK to data delay
-
20
T_OH
Data hold from CE, OE/RESET, or CLK
T_DF
CE or OE/RESET to data float delay⁽²⁾
0
-
-
25
T_CYC
T_LC
Clock periods
CLK Low time⁽³⁾
50
-
10
-
T_HC
T_SCE
CLK High time⁽³⁾
CE setup time to CLK (to guarantee proper counting)⁽³⁾
10
-
25
-
T_HCE
CE High time (to guarantee proper counting)
2
-
T_HOE OE/RESET hold time (guarantees counters are reset)
25
-
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
5. If T_HCE High < 2 µs, T_CE = 2 µs.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
ns
DS125 (v1.0) December 16, 2003
www.xilinx.com
11
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