XQ18V04_03 Datasheet, PDF (14/15 Pages) Xilinx, Inc – IEEE Std 1149.1 boundary-scan (JTAG) support

QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
Table 14: Pin Names and Descriptions (pins not listed are “no connect”) (Continued)
Pin
Name
CF
Boundary
Scan
Order
22
21
CEO
13
14
GND
TMS
TCK
TDI
TDO
V_CCINT
V_CCO
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
TEST MODE
SELECT
TEST CLOCK
TEST DATA IN
TEST DATA
OUT
Pin Description
Allows JTAG CONFIG instruction to initiate FPGA
configuration without powering down FPGA. This is an
open-drain output that is pulsed Low by the JTAG CONFIG
command.
Chip Enable Output (CEO) is connected to the CE input of
the next PROM in the chain. This output is Low when CE is
Low and OE/RESET input is High, AND the internal
address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND is the ground connection.
The state of TMS on the rising edge of TCK determines the
state transitions at the Test Access Port (TAP) controller.
TMS has an internal 50 Kohm resistive pull-up on it to
provide a logic "1" to the device if the pin is not driven.
This pin is the JTAG test clock. It sequences the TAP
controller and all the JTAG test and programming
electronics.
This pin is the serial input to all JTAG instruction and data
registers. TDI has an internal 50 Kohm resistive pull-up on
it to provide a logic "1" to the system if the pin is not driven.
This pin is the serial output for all JTAG instruction and data
registers. TDO has an internal 50 Kohm resistive pull-up on
it to provide a logic "1" to the system if the pin is not driven.
Positive 3.3V supply voltage for internal logic and input
buffers.
Positive 3.3V or 2.5V supply voltage connected to the
output voltage drivers.
R
Pin Number
44-pin
VQFP
10
21
6, 18, 28, 41
5
7
3
31
17, 35, 38
8, 16, 26, 36
14
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