XQ18V04_03 Datasheet, PDF (4/15 Pages) Xilinx, Inc – IEEE Std 1149.1 boundary-scan (JTAG) support

QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
R
DOUT
FPGA
Modes*
VCC
4.7K
VCC
**
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
OPTIONAL
Slave FPGAs
with identical
configurations
Vcc Vcco
DIN
CCLK
DONE
VCC VCCO
DATA
First
CLK _PROM
CE
CEO
DATA
CLK
CE
Cascaded
PROM
INIT
OE/RESET
OE/RESET
PROGRAM
CF
CF
(Low Resets the Address Pointer)
*For Mode pin connections, refer to the appropriate FPGA data sheet.
**Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others.
Master Serial Mode
I/O*
I/O*
VCC VCCO
CS
Modes***
WRITE
Virtex
1K ^1K
Select MAP
VCC
NC BUSY
**
External Osc
3.3V
4.7K
VCC VCCO
XQ18V04
CCLK
CLK
PROGRAM D[0:7]
8
D[0:7]
CEO
DONE
INIT
CE
CF
OE/RESET
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
**Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others.
***For Mode pin connections, refer to the appropriate FPGA data sheet.
Virtex Select MAP Mode
VCC
VCC VCCO
4.7K
VCC VCCO
8
D[0:7]
CEO
CE ^{XQ18V04 CF}
OE/RESET
CLK
VCC
4.7K
VCC
M0 M1
CS1
DOUT
XQ4000XL
D[0:7]
PROGRAM DONE
INIT _CCLK
M0 M1
CS1
DOUT
Optional
Daisy-chained
XQ4000XL
D[0:7]
PROGRAM DONE
INIT
CCLK
External Osc
XQ4000XL Express Mode
To Additional
Optional
Daisy-chained
Devices
To Additional
Optional
Daisy-chained
Devices
DS082_05_120103
Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode (c) XQ4000XL Express Mode
(dotted lines indicate optional connection)
4
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DS125 (v1.0) December 16, 2003
1-800-255-7778
Advance Product Specification