XQ18V04_03 Datasheet, PDF (7/15 Pages) Xilinx, Inc – IEEE Std 1149.1 boundary-scan (JTAG) support

R
QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
IEEE 1149.1 Boundary Scan (JTAG)
The XQ18V04 is fully compliant with the IEEE Std. 1149.1
Boundary Scan, also known as JTAG. A Test Access Port
(TAP) and registers are provided to support all required
boundary-scan instructions, as well as many of the optional
instructions specified by IEEE Std. 1149.1. In addition, the
JTAG interface is used to implement in-system program-
ming (ISP) to facilitate configuration, erasure, and verifica-
tion operations on the XQ18V04 device.
Table 5 lists the required and optional boundary-scan
instructions supported in the XQ18V04. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
Table 5: Boundary Scan Instructions
Boundary-Scan Binary
Command
Code [7:0]
Description
Required Instructions
BYPASS
11111111 Enables BYPASS
SAMPLE/
PRELOAD
00000001
Enables
boundary-scan
SAMPLE/PRELOAD
operation
EXTEST
00000000
Enables
boundary-scan
EXTEST operation
Optional Instructions
CLAMP
11111010
Enables
boundary-scan
CLAMP operation
HIGHZ
11111100
All outputs in
high-impedance state
simultaneously
IDCODE
11111110 Enables shifting out
32-bit IDCODE
USERCODE
11111101 Enables shifting out
32-bit USERCODE
XQ18V04 Specific Instructions
CONFIG
11101110
Initiates FPGA
configuration by
pulsing CF pin Low
Instruction Register
The Instruction Register (IR) for the XQ18V04 is eight bits
wide and is connected between TDI and TDO during an
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded
with a fixed instruction capture pattern. This pattern is
shifted out onto TDO (LSB first), while an instruction is
shifted into the instruction register from TDI. The detailed
composition of the instruction capture pattern is illustrated
in Figure 6.
The ISP Status field, IR[4], contains logic "1" if the device is
currently in ISP mode; otherwise, it will contain logic "0".
The Security field, IR[3], will contain logic "1" if the device
has been programmed with the security option turned on;
otherwise, it will contain logic "0".
IR[7:5] IR[4] IR[3] IR[2] IR[1:0]
TDI-> 0 0 0 ISP Security 0
Status
0 1 ->TDO
Notes:
1. IR[1:0] = 01 is specified by IEEE Std. 1149.1.
Figure 6: Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Boundary-Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST,
SAMPLE/PRELOAD, and CLAMP instructions. Each output
pin on the XQ18V04 has two register stages that contribute
to the boundary-scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI con-
trols and observes the output state, and the second stage
closest to TDO controls and observes the High-Z enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for examina-
tion by using the IDCODE instruction. The IDCODE is avail-
able to any other system component via JTAG.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (50h for the XQ18V04)
a = the ISP PROM product ID (26h for the XQ18V04)
c = the company code (49h for Xilinx)
Note: The LSB of the IDCODE register is always read as
logic "1" as defined by IEEE Std. 1149.1.
DS125 (v1.0) December 16, 2003
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