XC18V00 Datasheet, PDF (8/21 Pages) Xilinx, Inc – XC18V00 Series In-System

XC18V00 Series In-System Programmable Configuration PROMs
R
Table 5 lists the IDCODE register values for the XC18V00
devices.
Table 5: IDCODES Assigned to XC18V00 Devices
ISP-PROM
IDCODE
XC18V01
05024093h or 05034093h
XC18V02
05025093h or 05035093h
XC18V04
05026093h or 05036093h
XC18V512
05023093h or 05033093h
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply informa-
tion about the device’s programmed contents. By using the
USERCODE instruction, a user-programmable identifica-
tion code can be shifted out for examination. This code is
loaded into the USERCODE register during programming of
the XC18V00 device. If the device is blank or was not
loaded during programming, the USERCODE register con-
tains FFFFFFFFh.
XC18V00 TAP Characteristics
The XC18V00 family performs both in-system programming
and IEEE 1149.1 boundary-scan (JTAG) testing via a single
4-wire Test Access Port (TAP). This simplifies system
designs and allows standard Automatic Test Equipment to
perform both functions. The AC characteristics of the
XC18V00 TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
TCK
TMS
TDI
TDO
T_CKMIN1,2
T_MSS
T_DIS
T_MSH
T_DIH
T_DOV
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4.
Table 6: Test Access Port Timing Parameters
Symbol
Parameter
Min
T_CKMIN1
TCK minimum clock period
100
T_CKMIN2
TCK minimum clock period, Bypass Mode
50
T_MSS
TMS setup time
10
T_MSH
TMS hold time
25
T_DIS
TDI setup time
10
T_DIH
TDI hold time
25
T_DOV
TDO valid delay
-
DS026_04_032702
Max
Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
25
ns
8
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DS026 (v4.0) June 11, 2003
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Product Specification