XC18V00 Datasheet, PDF (12/21 Pages) Xilinx, Inc – XC18V00 Series In-System

XC18V00 Series In-System Programmable Configuration PROMs
R
Reset Activation
On power up, OE/RESET is held low until the XC18V00 is
active (1 ms). OE/RESET is connected to an external resis-
tor to pull OE/RESET HIGH releasing the FPGA INIT and
allowing configuration to begin. If the power drops below
2.0V, the PROM resets. OE/RESET polarity is not program-
mable. See Figure 8 for power-up requirements.
3.6V
Recommended Operating Range
3.0V
Recommended
V_CCINT Rise
Time
remains in a high-impedance state regardless of the state of
the OE input. JTAG pins TMS, TDI and TDO can be in a
high-impedance state or High. See Table 7.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3V. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V V_CCINT power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V_CCINT), and the output power sup-
ply (V_CCO) can have power applied in any order. This
makes the PROM devices immune to power supply
sequencing issues.
0V
0ms 1ms
Time (ms)
50ms
ds026_10_061103
Figure 8: V_CCINT Power-Up Requirements
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The address is reset. The output
Customer Control Bits
The XC18V00 PROMs have various control bits accessible
by the customer. These can be set after the array has been
programmed using “Skip User Array” in Xilinx iMPACT soft-
ware. The iMPACT software can set these bits to enable the
optional JTAG read security, parallel configuration mode, or
CF-->D4 pin function. See Table 7.
Table 7: Truth Table for PROM Control Inputs
Control Inputs
OE/RESET
CE
High
Low
Internal Address
If address < TC⁽¹⁾: increment
If address > TC⁽¹⁾: don’t change
Low
Low
Held reset
High
High
Held reset
Low
High
Held reset
Notes:
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
DATA
Active
High-Z
High-Z
High-Z
High-Z
Outputs
CEO
High
Low
High
High
High
I_CC
Active
Reduced
Active
Standby
Standby
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DS026 (v4.0) June 11, 2003
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Product Specification