XC18V00 Datasheet, PDF (2/21 Pages) Xilinx, Inc – XC18V00 Series In-System

XC18V00 Series In-System Programmable Configuration PROMs
R
Pinout and Pin Description
Table 1 provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC
packages.
Table 1: Pin Names and Descriptions
Pin
Name
Boundary
Scan
Order
Function
Pin Description
D0
4
DATA OUT D0 is the DATA output pin to provide data
for configuring an FPGA in serial mode.
3
OUTPUT
ENABLE
D1
6
DATA OUT D0-D7 are the output pins to provide
parallel data for configuring a Xilinx
5
OUTPUT _{FPGA in Slave-Parallel/SelectMap mode.}
ENABLE _{D1-D7 remain in HIGHZ state when the}
D2
2
DATA OUT ^{PROM operates in serial mode.}
1
OUTPUT
ENABLE
D1-D7 can be left unconnected when the
PROM is used in serial mode.
D3
8
DATA OUT
7
OUTPUT
ENABLE
D4
24
DATA OUT
23
OUTPUT
ENABLE
D5
10
DATA OUT
9
OUTPUT
ENABLE
D6
17
DATA OUT
16
OUTPUT
ENABLE
D7
14
DATA OUT
13
OUTPUT
ENABLE
CLK
0
DATA IN Each rising edge on the CLK input
increments the internal address counter if
both CE is Low and OE/RESET is High.
OE/
20
DATA IN When Low, this input holds the address
RESET
counter reset and the DATA output is in a
19
DATA OUT _{high-impedance state. This is a}
18
OUTPUT ^{bidirectional open-drain pin that is held}
ENABLE ^{Low while the PROM is reset. Polarity is}
NOT programmable.
CE
15
DATA IN When CE is High, the device is put into
low-power standby mode, the address
counter is reset, and the DATA pins are
put in a high-impedance state.
44-pin
VQFP
40
29
42
27
9
25
14
19
43
13
15
44-pin
PLCC
2
20-pin
SOIC &
PLCC
1
35
16
4
2
33
15
15
7⁽¹⁾
31
14
20
9
25
12
5
3
19
8
21
10
2
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DS026 (v4.0) June 11, 2003
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Product Specification