XC18V00 Datasheet, PDF (18/21 Pages) Xilinx, Inc – XC18V00 Series In-System

XC18V00 Series In-System Programmable Configuration PROMs
R
AC Characteristics Over Operating Conditions When Cascading for XC18V01 and
XC18V512
OE/RESET
CE
CLK
DATA
CEO
TCDF
Last Bit
TOCK
TOCE
TOOE
First Bit
DS026_07_020300
Symbol
Description
Min
Max
Units
T_CDF
T_OCK
T_OCE
T_OOE
CLK to data float delay^(2,3)
CLK to CEO delay⁽³⁾
CE to CEO delay⁽³⁾
OE/RESET to CEO delay⁽³⁾
-
25
ns
-
20
ns
-
20
ns
-
20
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
18
www.xilinx.com
DS026 (v4.0) June 11, 2003
1-800-255-7778
Product Specification