XC18V00 Datasheet, PDF (20/21 Pages) Xilinx, Inc – XC18V00 Series In-System

XC18V00 Series In-System Programmable Configuration PROMs
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Revision History
The following table shows the revision history for this document.
Date
2/9/99
8/23/99
9/1/99
9/16/99
01/20/00
02/18/00
04/04/00
06/29/00
11/13/00
01/15/01
04/04/01
04/30/01
06/11/01
09/28/01
11/12/01
12/06/01
02/27/02
03/15/02
03/27/02
06/14/02
07/24/02
09/06/02
10/31/02
Version
1.0
1.1
1.2
1.3
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Revision
First publication of this early access specification
Edited text, changed marking, added CF and parallel load
Corrected JTAG order, Security and Endurance data.
Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF
description, 256 Kbit and 128 Kbit devices.
Added Q44 Package, changed XC18xx to XC18Vxx
Updated JTAG configuration, AC and DC characteristics
Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to
FPGA table.
Removed XC18V128 and updated format. Added AC characteristics for XC18V01,
XC18V512, and XC18V256 densities.
Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: T_SCE units to ns, T_HCE
CE High time units to µs. Removed Standby Mode statement: “The lower power standby
modes available on some XC18V00 devices are set by the user in the programming
software”. Changed 10,000 cycles endurance to 20,000 cycles.
Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP
PROM product ID from 06h to 26h.
Updated Figure 6, Virtex SelectMAP mode; added XC2V products to Compatible PROM
table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years;
Updated Figure 6: removed Virtex-E in Note 2, fixed SelectMAP mode connections.
Under AC Characteristics Over Operating Conditions for XC18V04 and XC18V02,
changed T_SCE from 25 ms to 25 ns.
AC Characteristics Over Operating Conditions for XC18V01 and XC18V512.
Changed Min values for T_SCE from 20 ms to 20 ns and for T_HCE from 2 ms to 2 µs.
Changed the boundary scan order for the CEO pin in Table 1, updated the configuration
bits values in the table under Xilinx FPGAs and Compatible PROMs, and added
information to the Recommended Operating Conditions table.
Updated for Spartan-IIE FPGA family.
Changed Figure 7(c).
Updated Table 2 and Figure 6 for the Virtex-II Pro family of devices.
Updated Xilinx software and modified Figure 6 and Figure 7.
Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new Figure 8 and Figure 9.
Made additions and changes to Table 2.
Changed last bullet under Connecting Configuration PROMs, page 9.
Multiple minor changes throughout, plus the addition of Pinout Diagrams, page 4 and
the deletion of Figure 9.
Made minor change on Figure 7 (b) and changed orientation of SO20 diagram on page 5.
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