XC18V00 Datasheet, PDF (10/21 Pages) Xilinx, Inc – XC18V00 Series In-System

XC18V00 Series In-System Programmable Configuration PROMs
R
VCCO VCCINT
(See Note 2)
VCCO VCCINT
(See Note 2)
J1
1
TDI
TMS
2
3
TCK
4
TDO
VCCINT
D0
VCCO
XC18V00
Cascaded
PROM
TDI
TMS
TCK
CLK
CE
CEO
OE/RESET
CF
GND
TDO
VCCINT
D0
VCCO
XC18V00
First
PROM
TDI
TMS
TCK
CLK
CE
CEO
OE/RESET
CF
GND
TDO
VCCO
(See Note 2)
4.7K
MODE PINS
(See Note 1)
DIN
DOUT
Xilinx
FPGA
VCCO
Master
4.7K
(See
Serial
Note
1)
CCLK
DONE
INIT
PROGRAM
TDI
TMS
TCK
TDO
MODE PINS
(See Note 1)
DIN
Xilinx
FPGA
Slave
Serial
CCLK
DONE
INIT
PROGRAM
TDI
TMS
TCK
TDO
Notes:
1For _{Mode pin connections and DONE pin pullup value, refer to appropriate FPGA data sheet.}
2For _{compatible voltages, refer to the appropriate FPGA data sheet.}
Figure 5: Configuring Multiple Devices in Master/Slave Serial Mode
DS026_08_061003
J1
1
TDI
TMS
2
3
TCK
4
TDO
(2)
VCCO VCCINT
(2)
VCCO VCCINT
VCCINT
VCCO
D[0:7](3)
XC18V00
Cascaded
PROM
TDI
TMS
TCK
CLK
CE
CEO
OE/RESET
CF
GND
TDO
VCCINT
VCCO
D[0:7] ⁽³⁾
XC18V00
First
PROM
TDI
TMS
TCK
CLK
CE
CEO
OE/RESET
CF
GND
TDO
VCCO⁽²⁾
4.7K
(1)
MODE PINS
D[0:7] ⁽³⁾
Xilinx
Virtex-II
VCCO⁽²⁾
FPGA
4.7K
(1)
Master
Serial/
SelectMAP
CCLK
DONE
INIT
PROGRAM
TDI
TMS
TCK
TDO
MODE PINS
**D[0:7]
Xilinx
Virtex-II
FPGA
Slave
Serial/
SelectMAP
CCLK
DONE
INIT
PROGRAM
TDI
TMS
TCK
TDO
Notes:
1 _{For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.}
2 _{For compatible voltges, refer to the appropriate FPGA data sheet.}
3 _{Master/Slave Serial Mode does not require D[1:7] to be connected.}
DS026_09_051003
Figure 6: Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes
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DS026 (v4.0) June 11, 2003
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Product Specification