XC18V00 Datasheet, PDF (3/21 Pages) Xilinx, Inc – XC18V00 Series In-System

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XC18V00 Series In-System Programmable Configuration PROMs
Table 1: Pin Names and Descriptions (Continued)
Pin
Name
CF
Boundary
Scan
Order
22
21
Function
Pin Description
DATA OUT
OUTPUT
ENABLE
Allows JTAG CONFIG instruction to
initiate FPGA configuration without
powering down FPGA. This is an
open-drain output that is pulsed Low by
the JTAG CONFIG command.
44-pin
VQFP
10
44-pin
PLCC
16
20-pin
SOIC &
PLCC
7⁽¹⁾
CEO
12
DATA OUT Chip Enable Output (CEO) is connected
21
27
13
to the CE input of the next PROM in the
11
OUTPUT _{chain. This output is Low when CE is Low}
ENABLE _{and OE/RESET input is High, AND the}
internal address counter has been
incremented beyond its Terminal Count
(TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
GND
GND is the ground connection.
6, 18, 28 & 3, 12, 24
11
41
& 34
TMS
MODE The state of TMS on the rising edge of
5
11
5
SELECT TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic “1” to the
device if the pin is not driven.
TCK
CLOCK This pin is the JTAG test clock. It
7
13
6
sequences the TAP controller and all the
JTAG test and programming electronics.
TDI
DATA IN This pin is the serial input to all JTAG
3
9
4
instruction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the system if the pin
is not driven.
TDO
DATA OUT This pin is the serial output for all JTAG
31
37
17
instruction and data registers. TDO has
an internal 50K ohm resistive pull-up on it
to provide a logic “1” to the system if the
pin is not driven.
V_CCINT
Positive 3.3V supply voltage for internal
logic.
17, 35 &
38⁽³⁾
23, 41 &
44⁽³⁾
18 & 20⁽³⁾
V_CCO
Positive 3.3V or 2.5V supply voltage
8, 16, 26 & 14, 22, 32
19
connected to the input buffers⁽²⁾ and
36
& 42
output voltage drivers.
NC
No connects.
1, 2, 4, 1, 6, 7, 8,
11, 12, 20, 10, 17, 18,
22, 23, 24, 26, 28, 29,
30, 32, 33, 30, 36, 38,
34, 37, 39, 39, 40, 43
44
Notes:
1. By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and route
the CF function to pin 7 in the Serial mode.
2. For devices with IDCODES 0502x093h, the input buffers are supplied by V_CCINT.
3. For devices with IDCODES, 0503x093h, these V_CCINT pins are no connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC
package and pin 20 in 20-pin SOIC and20-pin PLCC packages.
DS026 (v4.0) June 11, 2003
www.xilinx.com
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Product Specification
1-800-255-7778