DS693 Datasheet, PDF (7/13 Pages) Xilinx, Inc – Integrated into Xilinx Embedded Development Kit

LogiCORE IP Virtex-5 APU Floating-Point Unit (v1.01a)
Table 1: PowerPC FP Instruction Set Support (Cont’d)
Instruction
Description
frsqrte
Recip. sqrt. estimate
fsel
Select (ternary operator)
mcrfs
Status/control register to condition register
mffs
Move from status/control register
mtfsb0
Move to status/control register
mtfsb1
Move to status/control register bit 1
mtfsf
Move to status/control register fields
mtfsfi
Move to status/control register immediate
Legend:
Yes = supported; No = not supported;
SP = operation performed in single-precision; NS = non-standard ⁽²⁾
Single Precision Double Precision
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Notes:
1. Double-precision store instructions can be issued to a single-precision FPU. Data will be converted on the fly between double- and single-precision formats
as necessary.
2. A single-precision FPU will treat the fcfid (convert from signed integer double-word to FP double) as if it were fcfiw (convert from signed integer word to FP
single). This behavior is non-standard, but allows hardware acceleration of format conversions that would not otherwise be possible in a single-precision unit.
If a program attempts to execute an unsupported floating-point instruction, there are two possible outcomes. If the
instruction belongs to one of the groups that can be disabled by the APU controller and this group has been
disabled, then an exception will be raised. Otherwise, the result is boundedly undefined.
Use the appropriate compiler flags to ensure that unsupported instructions are not generated by the compiler. See
the Xilinx Embedded System Tools Reference Manual for details.
For information about how to disable decoding of unsupported instructions, see the Virtex-5 Embedded Processor
Block for PowerPC 440 Designs Reference Manual.
Floating-Point Status and Control Register
The Floating-Point Status and Control Register (FPSCR) is implemented as described in the PowerPC Processor
Book-E specification. All instructions for explicit access to this register are supported in all configurations. All
FPSCR instructions take approximately 10 FCB clock cycles to execute.
The following lists some minor deviations from the Book-E-specified behavior. Most of these items relate to how the
FPSCR bits are set as a by-product of executing arithmetic instructions, and result from the implementation
limitations described in the section Floating-Point Status and Control Register, page 7.
• Bit 38 - Inexact exception. Always reads as zero.
• Bit 39 - Invalid operation (Signalling NaN). All NaNs are currently treated as quiet NaNs. This bit always
reads as zero.
• Bit 45 - Fraction Rounded. Always reads as zero.
• Bit 46 - Fraction Inexact. Always reads as zero.
• Bit 61 - non-IEEE mode. This bit is ignored. Only IEEE mode is supported.
The FPU supports all four of the Floating-Point Exception modes defined by Book-E:
• Exceptions Disabled mode provides the highest performance. When exceptional conditions arise, they are
recorded in the FPSCR and can be explicitly examined later by the software.
DS693 March 1, 2011
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Product Specification