DS693 Datasheet, PDF (12/13 Pages) Xilinx, Inc – Integrated into Xilinx Embedded Development Kit

LogiCORE IP Virtex-5 APU Floating-Point Unit (v1.01a)
Table 4: FPU Operator Latencies and Frequencies
Instruction
C_LATENCY = 0 (high speed)
Single
Double
Fused Multiply-Add/Sub
9
12
Move, Abs, Neg, etc.
1
1
Round
N/A
6
Compare
4
4
Maximum frequency (-1)
200MHz
200MHz
Maximum frequency (-2)
225MHz
225MHz
C_LATENCY = 1 (low latency)
Single
Double
6
8
1
1
N/A
4
4
4
140MHz
140MHz
160MHz
160MHz
A floating-point instruction can be issued on every FPU clock cycle (usually every other CPU clock cycle).
The divide and square root operators are sequential. This means that at any given time only a maximum of one
divide operation and one square root operation can be in progress. In contrast, the add, multiply, convert, and
round operators are pipelined. At any given time, the maximum number of each of these operations that can be in
progress is equal to the depth of that operator's pipeline as specified in Table 4.
The PowerPC processor architecture does not specify instructions for moving data between CPU registers (GPRs)
and floating-point registers (FPRs). All FPU data transfers are therefore between the FPRs and main memory (or
data cache, if used). A data load from cache can be performed in a single FPU clock cycle. Note that the APU
controller cannot process more than one outstanding load instruction, so this latency occurs on each load.
Floating-point store operations take three FPU clock cycles (assuming that there is no data dependency on a
previous instruction whose result is still outstanding).
Reference Documents
1. Virtex-5 Embedded Processor Block for PowerPC 440 Designs Reference Manual
2. Book E: Enhanced PowerPC Architecture. 2002. IBM Corporation.
3. Hennessy, John L. and David A. Patterson. 1996. Computer Architecture: A Quantitative Approach. San
Francisco: Morgan Kaufmann.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE^® Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
DS693 March 1, 2011
www.xilinx.com
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Product Specification