DS693 Datasheet, PDF (4/13 Pages) Xilinx, Inc – Integrated into Xilinx Embedded Development Kit

LogiCORE IP Virtex-5 APU Floating-Point Unit (v1.01a)
Additionally, the optional negation of the addition result available in the fnmadd(s)/fnmsub(s) instructions is
applied to the operands at the input of the addition instead. The resulting behavior is identical, except that a
zero result will always have a positive sign.
• Default Results. The default IEEE result is always delivered to the destination register regardless of any
exception resulting from the instruction. The following are not supported:
• The suppression of execution for enabled Invalid Operation Exceptions and enabled Zero Divide
exceptions
• The production of adjusted intermediate results in the case of enabled Overflow/Underflow exceptions
• NaN handling. The FPU treats all not-a-number (NaN) values as quiet NaNs, which do not cause exceptions.
When a floating-point operation results in a NaN because one of the inputs was a NaN, the input NaN is not
propagated to the output; the default quiet NaN value is provided. This value is 0x7ff8000000000000 in double
precision, and 0x7f800000 in single precision.
All of the above deviations apply to both the single-precision and double-precision variants of the FPU. See
PowerPC Instruction Set Support, page 5 for a description of those deviations from the Book-E model that apply
only to the single-precision FPU. Because the single-precision FPU has a narrower register file than the Book-E
standard requires, it cannot be used with off-the-shelf compilers or operating systems without modifications.
Functional Description
Fabric Coprocessor Bus (FCB) Interface
The FPU is connected to the PowerPC processor via the Auxiliary Processor Unit (APU) interface. This dedicated
co-processor port is tightly coupled with the PowerPC processor internal instruction pipeline and memory
subsystem, which makes it ideal for connecting co-processors that execute instructions from the PowerPC
instruction stream, such as an FPU.
A block of logic known as the APU controller mediates between the PowerPC processor and the fabric co-processor.
The bus connecting the FPU to the APU controller is known as the Fabric Coprocessor Bus, or FCB.
The data buses within the FCB which carry data to and from the memory system are 128 bits wide. The instruction
bus is 32 bits wide, as are the operand data buses which carry data to and from the PowerPC processor register file
(these are not used by the FPU). There are a number of other control signals involved in an FCB transaction. Full
details of the APU/FCB interface can be found in the Virtex-5 Embedded Processor Block for PowerPC 440 Designs
Reference Manual listed in the Reference Documents section.
It is possible to connect multiple co-processors to the FCB. However, due to the additional multiplexing logic
required, doing so will adversely affect the maximum clock frequency of the system. For the highest possible
performance, it is recommended that the FPU is the only co-processor attached to the APU controller.
The APU controller allows the FCB (and thus the FPU) to run at a different speed from the CPU itself. Any integer
FCB:CPU clock ratio between 1:1 and 1:16 is a valid configuration. The high-speed variant of the FPU
(C_LATENCY_CONF=0) is optimized for operation at 200 MHz on speed grade 1 devices, which gives a 1:2 clock
ratio when the PowerPC is operated at its maximum frequency (400 MHz on speed grade 1). The low-latency
variant (C_LATENCY_CONF=1) is optimized for 133MHz operation, giving a 1:3 clock ratio.
When running in Exceptions Disabled mode the FPU can accept an instruction on every APU clock cycle, provided
that the APU controller can sustain this transfer rate and that FPU execution does not need to stall due to data
dependencies. All instructions can be acknowledged within a single clock cycle with the exception of store
operations which take at least three clock cycles.
DS693 March 1, 2011
www.xilinx.com
4
Product Specification