DS693 Datasheet, PDF (2/13 Pages) Xilinx, Inc – Integrated into Xilinx Embedded Development Kit

LogiCORE IP Virtex-5 APU Floating-Point Unit (v1.01a)
Functional Overview
The APU Floating-Point Unit comprises execution units, a register file, bus interface and all the control logic
necessary to manage the execution of floating-point instructions. Figure 1 provides an overview of the
Floating-Point Unit (FPU) architecture.
X-Ref Target - Figure 1
FCB2 Bus
FCB2
Bus
Interface
Execution
Control
and
Decode
Logic
Register File
and
Forwarding
Mov, Abs, Neg
Add/Sub/Convert
Compare
Multiply
FPSCR
Divide
Square Root
Round
DS693_01_102908
Figure 1: Top-level APU Floating-Point Coprocessor Architecture
Note that the rounding logic, which converts double-precision results to single precision, is not present in the
single-precision variant of the FPU.
Applications
The APU Floating-Point Unit augments the capabilities of the PowerPC 440 processor core with support for
floating-point instructions. Many software applications make use of floating-point arithmetic, whether for
occasional calculations or for intensive computation kernels. Some examples of application areas where
floating-point arithmetic can be useful are:
• Digital signal processing of high-quality audio or video signals where a very large dynamic range is needed to
retain fidelity.
• Matrix inversion in wireless communications and radar where algorithms such as QR decomposition and
singular value decomposition are numerically unstable without sufficient dynamic range.
• Interpolation and extrapolation where quantization errors can lead to sub-optimal results.
• Digital signal processing tasks, particularly spectral methods such as FFT, in which the required range and
precision of data samples may be difficult to predict at design time.
DS693 March 1, 2011
www.xilinx.com
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Product Specification