DS693 Datasheet, PDF (1/13 Pages) Xilinx, Inc – Integrated into Xilinx Embedded Development Kit

DS693 March 1, 2011
LogiCORE IP Virtex-5 APU
Floating-Point Unit (v1.01a)
Product Specification
Introduction
The Virtex^®-5 Auxiliary Processor Unit (APU)
Floating-Point Unit is an optimized FPU designed for
the PowerPC^® 440 embedded microprocessor of the
Virtex-5 FXT FPGA family. The FPU implementation
provides support for IEEE-754 floating-point arithmetic
operations in single or double precision.
The FPU is not Power ISA compliant and does not
support every instruction defined by the PowerPC
processor instruction set architecture. The
double-precision FPU configuration will support any
compiler that allows graphics instructions (fsel, fres and
frsqrte) to be disabled, which makes it compatible with
all compilers and operating systems that currently
support the Virtex-5 FXT family.
The FPU is tightly coupled to the PowerPC processor
core with the APU interface. Software applications can
use native PowerPC processor floating-point
instructions to achieve typical speedups of 6x over
software emulation.
Features
• Compatible with the IEEE-754 standard for single-
and double-precision floating-point arithmetic,
with minor and documented exceptions
• Decodes and executes standard PowerPC
processor floating-point instructions
• Optimized for 2:1 and 3:1 APU:CPU clock ratios,
allowing PowerPC processor to operate at
maximum frequency
• Uses autonomous instruction issue to hide
arithmetic latency and decrease cycles per
instruction
• Optimized implementation leverages Virtex-5
high-performance DSP features
• Integrated into Xilinx Embedded Development Kit
(EDK) design flow
• Single-precision-only option also provided (works
with Xilinx-provided GCC compiler)
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
Virtex-5
Supported User
Interfaces
APU
Resources
Resources
Used
LUT-Reg
Pairs
DSP Blocks
Block
RAMs
Single
2620
3
0
Double
4950
13
0
-1 (high speed)
200 MHz
Clock Speed
-1 (low latency)
-2 (high speed)
140 MHz
225 MHz
-2 (low latency)
160 MHz
Provided with Core
Documentation
Product Specification
Design Files
VHDL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
Automatically generated UCF
Simulation
Model
VHDL
Tested Design Tools
Design Entry
Tools
13.1 EDK
Simulation
ModelSim PE/SE 6.6c or higher
Synthesis Tools
XST
Support
Provided by Xilinx, Inc.
© Copyright 2008-2009, 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the
property of their respective owners.
DS693 March 1, 2011
www.xilinx.com
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Product Specification