DS693 Datasheet, PDF (3/13 Pages) Xilinx, Inc – Integrated into Xilinx Embedded Development Kit

LogiCORE IP Virtex-5 APU Floating-Point Unit (v1.01a)
• Statistical processing and ad hoc calculations, where floating-point is often the simplest way to avoid integer
overflow and rounding errors.
Increased Processing Capacity
The APU Floating-Point Unit increases the processing capacity of a PowerPC processor-based embedded system in
the following ways:
1. Hardware floating-point operations complete faster than the equivalent software emulation routines, making
floating-point arithmetic faster.
2. In software, only one floating-point operation can be in progress at a time. The floating-point operators within
the FPU are pipelined so that multiple floating-point calculations can proceed in parallel. This parallelism in a
floating-point algorithm can lead to dramatic speedups.
3. The FPU is autonomous; therefore, the PowerPC processor internal pipeline can continue to execute integer
instructions while floating-point operations are handled by the FPU in parallel.
Operating System Support
The double-precision full-featured FPU variant is sufficiently compliant with the standard that it should be directly
compatible with off-the-shelf third-party compilers, operating systems and application software that expect a
Book-E compliant FPU.
For the single-precision variant of the FPU, some modification of the compiler, operating system and software is
likely to be necessary. Xilinx can provide supplementary information, including patches for the GNU tool-chain, on
request.
In order for FPU instructions to be decoded by the APU controller and executed by the FPU, the FPU enable bit
must be set in the Machine State register. See the Virtex-5 Embedded Processor Block for PowerPC 440 Designs
Reference Manual listed in the Reference Documents section for details of this and other system configuration bits.
Attempting to execute an FPU instruction when this bit is not set will result in an unsupported instruction
exception.
To allow efficient data transfer rates on the APU interface to be maintained, the FPU supports operation in
big-endian mode only. The APUFCMENDIAN signal from the APU controller is ignored.
IEEE 754-1985 / Book-E Standard Compatibility
The double-precision Floating-Point Unit complies with the majority of the IEEE-754 and Book-E requirements for
binary floating-point arithmetic, including support for both single and double precision and all four standard
rounding modes. This makes it suitable for use with most off-the-shelf compilers and operating systems which
expect a Book-E compliant floating-point unit.
The following list details FPU deviations from these standards:
• Denormalized Numbers. The standard defines a means of representing very small numbers by allowing
significands of the form "0.x" in addition to the usual “1.x” used by normalized floating-point numbers. These
are numbers with magnitude less than 2^-126 (single precision) or 2^-1022 (double precision). The FPU treats such
numbers as zero. If an operation is presented with such a tiny value, it will be treated as an
equivalently-signed zero. If an operation would produce such a tiny value, the FPU will indicate an arithmetic
underflow and produce a zero result instead.
• Multiply-Add. Book-E asks that the multiply part of a multiply-add operation should not round its result
before supplying it to the addition part, but the FPU does not operate in this way. The combined operation is
simply the equivalent of performing individual multiply and add instructions. This may have implications for
certain numerical algorithms that rely on the extra accuracy of the intermediate result in this case.
DS693 March 1, 2011
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Product Specification