DS693 Datasheet, PDF (5/13 Pages) Xilinx, Inc – Integrated into Xilinx Embedded Development Kit

LogiCORE IP Virtex-5 APU Floating-Point Unit (v1.01a)
Register File
The register file contains 32 floating-point registers. The width of these registers and of the internal data path
depends on the precision selected – either 32 bits (single) or 64 bits (double). Regardless of the precision chosen, the
APU/FCM interface ports remain 128 bits wide, so data transfers of any size require only a single clock cycle.
Figure 2 shows the layout of the fields that compose a floating-point number within the binary word(s) for each
precision. The most significant bit is numbered as bit zero.
X-Ref Target - Figure 2
01
21
31
Double s e e e e e e e e e e e f f f f f f f f f f f f f f f f f f f f
32
63
f f f ff f ff ff f f ff f f f f f f ff f f ff f f ff f f
01
9
31
Single s e e e e e e e e f f f f f f f f f f f f f f f f f f f f f f f
Legend:
s = sign bit
e = exponent bits
f = fraction (mantissa) bits
DS693_02_102908
Figure 2: Supported Floating-Point Format Layout
PowerPC Instruction Set Support
The FPU supports both single and double precision. Table 1 details which instructions are supported by each
configuration. For more information about the PowerPC floating-point instruction set, see Book E: Enhanced Power
PC Architecture Version 1.0.
In general, the entire floating-point instruction set is supported, with the following exceptions:
• No FPU configurations support the instructions fres, frsqrte and fsel. Most compilers do not use these
instructions unless specifically requested.
• The single-precision FPU:
• Does not support conversions from floating-point to integer double-word formats, like fctid and fctidz, nor
the round double to single operation frsp.
• Interprets the fcfid instruction (convert from integer double-word) as a non-standard convert from integer
word. This is because the source register is only 32 bits wide.
• Accepts double-precision arithmetic operations but will execute them in single precision.
Both single and double-precision FPUs support both single and double-precision load and store operations. When
transferring double-precision data into or out of a single-precision FPU, the values are silently expanded or
truncated as necessary (without rounding or renormalization).
DS693 March 1, 2011
www.xilinx.com
5
Product Specification