DS646 Datasheet, PDF (7/11 Pages) Xilinx, Inc – Integrated Logic Analyzer

LogiCORE IP ChipScope Pro Integrated Controller (ICON) (v1.05a)
module chipscope_vio
(
inout [35: 0] CONTROL,
input [ 7: 0] ASYNC_IN);
endmodule
Xilinx Platform Studio
Using ICON Core in XPS
The ICON core can be inserted into an embedded processor design using the Xilinx Platform Studio (XPS). In this
case, the ICON core depends on a BSCAN component instance whose interface is exported by the OPB_MDM
peripheral component (see Figure 4).
X-Ref Target - Figure 4
OPB MDM
ChipScope Pro
ICON Core
CAPTURE_IN
TDI_IN
RESET_IN
SHIFT_IN
UPDATE_IN
SEL_IN
DRCK_IN
TDO_OUT
CAPTURE_IN
TDI_IN
RESET_IN
SHIFT_IN
UPDATE_IN
SEL_IN
DRCK_IN
TDO_OUT
CONTROL0
CONTROL1
CONTROL2
CONTROL3
CONTROL4
CONTROL5
CONTROL6
CONTROL7
CONTROL8
CONTROL9
CONTROL10
CONTROL11
CONTROL12
CONTROL13
CONTROL14
Connect to
one or more
IBA, ILA, etc.
Figure 4: ICON Core Component in EDK XPS Design
DS646_04
In EDK, the ICON core is integrated into the tool using a Tcl script. When the EDK Hardware Platform Generator
(Platgen) tool runs, the Tcl script is called and the script internally calls the CORE Generator™ (Coregen) tool in the
command line mode. The Tcl script provides the CORE Generator software a parameters file (.xco) to generate the
ICON core netlist. The Tcl script also generates an HDL wrapper to match the ICON ports based on the core
parameters listed in Figure 4. The XST synthesis tool is used for synthesizing the wrapper HDL generated for the
ICON core. The NGC netlist outputs from XST and ChipScope Pro Core Generator are subsequently incorporated
into the Xilinx ISE^® tool suite for actual device implementation.
DS646 June 22, 2011
www.xilinx.com
7
Product Specification