DS646 Datasheet, PDF (1/11 Pages) Xilinx, Inc – Integrated Logic Analyzer

DS646 June 22, 2011
LogiCORE IP ChipScope
Pro Integrated Controller
(ICON) (v1.05a)
Product Specification
Introduction
The LogiCORE™ IP ChipScope™ Pro Integrated
CONtroller core (ICON) provides an interface between
the JTAG Boundary Scan (BSCAN) component of the
FPGA and the ChipScope Pro cores, including the
following types of cores:
• Integrated Logic Analyzer (ILA)
• Virtual Input/Output (VIO)
• ChipScope AXI Monitor
• Agilent Trace Core 2 (ATC2)
These debug cores are directly attached to the ICON
core control ports. Once generated, the ICON core is
easily instantiated and connected to these cores using
standard Verilog and VHDL syntax. The ICON core can
be added to an embedded processor system design
using the Xilinx Embedded Development Kit (EDK)
tools. Finally, through the core inserter interface the
ICON core is automatically added without requiring
any change to the Verilog or VHDL sources.
Features
• Provides a communication path, using the JTAG
port, between the ChipScope Pro Analyzer
software and the ILA, VIO, ATC2, and the
ChipScope AXI monitor cores
• Connects to the JTAG chain through the USER scan
chain feature of the BSCAN component
• Supports up to 15 ChipScope debug cores attached
to the ICON control ports
• Supports internal or external BSCAN connection
LogiCORE IP Facts Table
Core Specifics
Supported Device
Family ⁽¹⁾
Artix-7⁽³⁾, Virtex-7⁽³⁾, Kintex-7⁽³⁾, Virtex-6,
Virtex-5, Virtex-4, Spartan-6/6L, Spartan-3E,
Spartan-3,
Spartan-3A/Spartan-3A DSP,
XA Spartan-3/3A DSP, XA Spartan-3E, XA
Spartan-6, XA Virtex-4,
Spartan-6Q/6QL, Virtex-4Q,
Virtex-5Q, Virtex-6Q/6QL
Supported User
Interfaces
Not applicable.
Provided with Core
Resources
Frequency
Configuration ⁽⁴⁾
LUTs
FFs
DSP
Slices
Block
RAMs
Max
Freq
Config1
90 108 0
0
398.867
MHz
Config2
317 335 0
0
384.919
MHz
Config3
541 559 0
0
380.055
MHz
Documentation
Product Specification
User Guide
Design Files
Netlist
Example Design
Verilog/VHDL
Test Bench
Provided
Constraints File
Xilinx Constraints
Simulation Model
Tested Design Tools ⁽²⁾
Not Provided
Design Entry Tools Core Generator tool, System Generator, XPS
Simulation
Not provided
Support
Provided by Xilinx, Inc.
Notes:
1. For a complete listing of supported derivative devices, see the
IDS Embedded Edition Derivative Device Support.
2. For a listing of the supported tool versions, see the ISE Design
Suite 13: Release Note Guide.
3. For more information, see DS180 7 Series FPGAs Overview.
4. For configuration details, see Table 4, page 10.
© Copyright 2008-2009, 2011 Xilinx, Inc. XILINX, the Xilinx logo, Kintex, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. All other trademarks are the property of their respective owners.
DS646 June 22, 2011
www.xilinx.com
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Product Specification