DS646 Datasheet, PDF (5/11 Pages) Xilinx, Inc – Integrated Logic Analyzer

LogiCORE IP ChipScope Pro Integrated Controller (ICON) (v1.05a)
Generating the Core
After entering the ICON core parameters, click Generate to create the ICON core files. After the ICON core has been
generated, a list of the generated files will appear in a separate window called "Readme <corename>".
Using the ICON Core
To instantiate the example ICON core HDL files into the design, use the following guidelines to connect the ICON
core port signals to various signals in your design:
• Connect one of the ICON core's unused CONTROL* port signals to a control port of only one ILA, VIO, or
ATC2 core instance in the design.
• Do not leave any unused CONTROL* ports of the ICON core unconnected as this will cause the
implementation tools to report an error. Instead, use an ICON core with the same number of CONTROL* ports
as you have ILA, VIO or ATC2 cores
Example 1: ICON Connection in VHDL and Example 2: ICON Connection in Verilog show how the ICON core is
connected in vhdl and verilog respectively. Note how the control bus control0 is attached to the control port of the
VIO. Note how in the Verilog example an empty module declaration was created ICON and VIO. This is used as a
black box declaration so that the synthesis tool properly accounts for the generated netlists.
Example 1: ICON Connection in VHDL
entity example_chipscope_icon is
end example_chipscope_icon;
architecture icon_arch of example_chipscope_icon iS
-----------------------------------------------------------------
--
-- Component declarations
--
---------------------------------------------------------------------
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_vio
port (
CONTROL : inout std_logic_vector(35 downto 0);
ASYNC_IN : in std_logic_vector(7 downto 0));
end component;
------------------------------------------------------------------
-- Local Signals
-------------------------------------------------------------------
signal control0 : std_logic_vector(35 downto 0);
begin
-------------------------------------------------------------------
--
-- ICON Pro core instance
--
-------------------------------------------------------------------
ICON_inst: chipscope_icon
port map (
CONTROL0 => control0);
-------------------------------------------------------------------
DS646 June 22, 2011
www.xilinx.com
5
Product Specification