DS646 Datasheet, PDF (4/11 Pages) Xilinx, Inc – Integrated Logic Analyzer

LogiCORE IP ChipScope Pro Integrated Controller (ICON) (v1.05a)
CORE Generator
The CORE Generator tool provides the ability to define and generate a customized ICON core to use with one or
more ILA, VIO, or ATC2 capture cores in HDL designs. The control ports can be customized (that is, the number of
cores to be connected to the ICON core); in addition, the use of the Boundary Scan primitive component can be
customized (for example, BSCAN_VIRTEX5) that is used for JTAG communication.
Generating an Example Design
The ICON core generator normally generates standard Xilinx CORE Generator output files only, such as netlist and
instantiation template files. To generate an example design that uses the ICON core, in addition to the normal
generated files, select the Generate Example Design check box. This parameter is stored as example_design in the
generated XCO parameter file.
Entering the Number of Control Ports
The ICON core can communicate with any combination of up to 15 ILA, VIO, or ATC2 capture core units at any
given time by controlling each core with a distinct control port. The number of control portsYou can be selected
from the Number of Control Ports pull-down list. This parameter is stored as number_control_ports in the
generated XCO parameter file.
Disabling the Boundary Scan Component Instance
The Boundary Scan primitive component (for example, BSCAN_VIRTEX5) is used to communicate with the JTAG
Boundary Scan logic of the target FPGA device. The Boundary Scan component extends the JTAG test access port
(TAP) interface of the FPGA device so that up to four internal scan chains can be created. The Boundary Scan
component is instantiated inside the ICON core by default. Use the Disable Boundary Scan Component Instance
check box, stored as use_ext_bscan in the generated XCO parameter file, to disable the instantiation of the
Boundary Scan component.
Selecting the Boundary Scan Chain
The Analyzer can communicate with the cores using either the USER1, USER2, USER3, or USER4 boundary scan
chains. If the Boundary Scan component is instantiated inside the ICON core, the user can select the desired scan
chain from the Boundary Scan Chain pull-down list. This parameter is stored as user_scan_chain in the generated
XCO parameter file.
Enabling Unused Boundary Scan Ports
This feature is only available for Spartan^®-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP devices. The Boundary
Scan primitive for Virtex^®-4, Virtex-5, Virtex-6, and Spartan-6, Artix™-7, Kintex™-7, and Virtex-7 devices
(including the variants of these families) can have only one of four sets of ports enabled at any given time.
The Boundary Scan primitive for Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP devices (including the
variants of these families) always has two sets of ports: USER1 and USER2. The ICON core uses only one of the
USER* scan chain ports for communication purposes, therefore, the unused USER* port signals are available for use
by other design elements, respectively. If the Boundary Scan component is instantiated inside the ICON core,
selecting the Enable Unused Boundary Scan Ports check box provides access to the unused USER* scan chain
interfaces of the Boundary Scan component. This parameter is stored as use_unused_bscan in the generated XCO
parameter file.
DS646 June 22, 2011
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Product Specification