DS646 Datasheet, PDF (2/11 Pages) Xilinx, Inc – Integrated Logic Analyzer

LogiCORE IP ChipScope Pro Integrated Controller (ICON) (v1.05a)
Functional Description
The ICON core provides an interface between the ChipScope Pro Analyzer tool and up to 15 ChipScope Pro target
cores (such as ILA, IBA, VIO, and ATC2) via the JTAG Boundary Scan port of the target FPGA. The ICON core
bridges the gap between the JTAG Boundary Scan TAP controller of the FPGA and the target cores using the USER
scan chains provided by the BSCAN primitive component of the FPGA. The ICON core is responsible for routing
various commands sent from the Analyzer tool to the intended target cores.
The ICON core can be configured to automatically include the BSCAN primitive component (see Figure 1) or to use
a BSCAN elsewhere in the design (see Figure 3, page 3). The ICON core can also route unused BSCAN USER scan
chains to port signals if the BSCAN is included in the ICON core and the FPGA device family supports multiple
USER scan chains per BSCAN component (see Figure 3, page 3).
The ICON core connection to the target cores is implemented as a dedicated bi-directional control port. This control
port includes JTAG clock, input and output data, and control signals necessary to configure and communicate with
the target core.
X-Ref Target - Figure 1
ChipScope Pro
ICON Core
CONTROL0
CONTROL1
CONTROL2
CONTROL3
CONTROL4
CONTROL5
CONTROL6
CONTROL7
CONTROL8
CONTROL9
CONTROL10
CONTROL11
CONTROL12
CONTROL13
CONTROL14
DS646_01
Figure 1: ICON Core with Internal BSCAN Component
DS646 June 22, 2011
www.xilinx.com
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Product Specification