XQ18V04 Datasheet, PDF (5/17 Pages) Xilinx, Inc – QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

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QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
V CC
GND
(a)
(b)
DS026_02_011100
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
IEEE 1149.1 Boundary-Scan (JTAG)
The XQ(R)18V04 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addi-
tion, the JTAG interface is used to implement in-system pro-
gramming (ISP) to facilitate configuration, erasure, and
verification operations on the XQ(R)18V04 device.
Table 3 lists the required and optional boundary-scan
instructions supported in the XQ(R)18V04. Refer to the
IEEE Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
Table 3: Boundary Scan Instructions
Boundary-Scan Binary
Command Code [7:0]
Description
Required Instructions
BYPASS
11111111 Enables BYPASS
SAMPLE/
PRELOAD
00000001
Enables boundary-scan
SAMPLE/PRELOAD
operation
EXTEST
00000000 Enables boundary-scan
EXTEST operation
Optional Instructions
CLAMP
11111010 Enables boundary-scan
CLAMP operation
HIGHZ
11111100
All outputs in
high-impedance state
simultaneously
IDCODE
11111110 Enables shifting out
32-bit IDCODE
USERCODE
11111101 Enables shifting out
32-bit USERCODE
XQ(R)18V04 Specific Instructions
CONFIG
11101110
Initiates FPGA
configuration by pulsing
CF pin Low
DS082 (v1.2) November 5, 2001
www.xilinx.com
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Preliminary Product Specification
1-800-255-7778