XQ18V04 Datasheet, PDF (2/17 Pages) Xilinx, Inc – QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
Pinout and Pin Description
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC1700L one-time programmable Serial PROM family.
Table 1: Pin Names and Descriptions (pins not listed are “no connect”)
Pin
Name
Boundary
Scan
Order
Function
Pin Description
44-pin 44-pin
VQFP CLCC
D0
4
3
DATA OUT D0 is the DATA output pin to provide data for configuring an 40
2
OUTPUT
FPGA in serial mode.
ENABLE
D1
6
5
DATA OUT
OUTPUT
ENABLE
D0-D7 are the output pins to provide parallel data for
configuring a Xilinx FPGA in Express/SelectMap mode.
29
35
D2
2
DATA OUT
42
4
1
OUTPUT
ENABLE
D3
8
DATA OUT
27
33
7
OUTPUT
ENABLE
D4
24
DATA OUT
9
15
23
OUTPUT
ENABLE
D5
10
DATA OUT
25
31
9
OUTPUT
ENABLE
D6
17
DATA OUT
14
20
16
OUTPUT
ENABLE
D7
14
DATA OUT
19
25
13
OUTPUT
ENABLE
CLK
0
DATA IN
Each rising edge on the CLK input increments the internal 43
5
address counter if both CE is Low and OE/RESET is High.
OE/
20
RESET
19
18
DATA IN
When Low, this input holds the address counter reset and 13
19
DATA OUT
the DATA output is in a high-impedance state. This is a
bidirectional open-drain pin that is held Low while the
OUTPUT
PROM is reset. Polarity is NOT programmable.
ENABLE
CE
15
DATA IN
When CE is High, this pin puts the device into standby
15
21
mode and resets the address counter. The DATA output pin
is in a high-impedance state, and the device is in low power
standby mode.
2
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DS082 (v1.2) November 5, 2001
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Preliminary Product Specification