XQ18V04 Datasheet, PDF (4/17 Pages) Xilinx, Inc – QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs
R
Xilinx FPGAs and Compatible PROMs
Device
XQV100
XQV(R)300
XQV(R)600
XQV(R)1000
XQV(R)600E
XQV(R)1000E
XQV(R)2000E
Configuration
Bits
781,216
1,751,808
3,607,968
6,127,744
3,961,632
6,587,520
10,159,648
XQ(R)18VO4
PROMs
1
1
1
2
1
2
3
Capacity
Devices
XQ(R)18V04
Configuration Bits
4,194,304
In-System Programming
In-System Programmable PROMs can be programmed indi-
vidually, or two or more can be daisy-chained together and
programmed in-system via the standard 4-pin JTAG proto-
col as shown in Figure 2. In-system programming offers
quick and efficient design iterations and eliminates unnec-
essary package handling or socketing of devices. The Xilinx
development system provides the programming data
sequence using either Xilinx JTAG Programmer software
and a download cable, a third-party JTAG development sys-
tem, a JTAG-compatible board tester, or a simple micropro-
cessor interface that emulates the JTAG instruction
sequence. The JTAG Programmer software also outputs
serial vector format (SVF) files for use with any tools that
accept SVF format and with automatic test equipment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
OE/RESET
The ISP programming algorithm requires issuance of a
reset that will cause OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130 device programmer. This provides the
added flexibility of using pre-programmed devices in board
design and boundary-scan manufacturing tools, with an
in-system programmable option for future enhancements
and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 2,000 in-system program/erase
cycles and a minimum data retention of ten years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorpo-
rate advanced data security features to fully protect the pro-
gramming data against unauthorized reading. Table 2
shows the security setting available.
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 2: Data Security Options
Default = Reset
Read Allowed
Program/Erase Allowed
Set
Read Inhibited via JTAG
Erase Allowed
4
www.xilinx.com
DS082 (v1.2) November 5, 2001
1-800-255-7778
Preliminary Product Specification