XQ18V04 Datasheet, PDF (1/17 Pages) Xilinx, Inc – QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs

R
DS082 (v1.2) November 5, 2001
Features
• In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
- Endurance of 2,000 program/erase cycles
- Program/erase over full military temperature range
• IEEE Std 1149.1 boundary-scan (JTAG) support
• Cascadable for storing longer or multiple bitstreams
• Dual configuration modes
- Serial Slow/Fast configuration (up to 33 MHz)
- Parallel (up to 264 Mbps at 33 MHz)
• Low-power advanced CMOS FLASH process
• 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals.
• 3.3V or 2.5V output capability
• Available in CC44 and VQ44 packages.
• Design support using the Xilinx Alliance™ and
Foundation™ series software packages.
• JTAG command initiation of standard FPGA
configuration.
• Available to Standard Microcircuit Drawing
5962-01525.
- For more information contact Defense Supply
Center Columbus (DSCC) at
http://www.dscc.dla.mil
CLK CE
QPro XQ18V04 (XQR18V04) QML
In-System Programmable
Configuration PROMs
Preliminary Product Specification
Radiation Hardenned XQR18V04
• Fabricated on Epitaxial Substrate
• Latch-Up Immune to >120 LET
• Guaranteed TID of 40 kRad(Si)
• Supports SEU Scrubbing
Description
Xilinx introduces the QPro™ XQ18V04 and XQR18V04
series of QML in-system programmable and radiation hard-
ened configuration PROMs. Initial devices in this 3.3V fam-
ily are a 4-megabit PROM that provide an easy-to-use,
cost-effective method for re-programming and storing large
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA D_IN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROMs DATA (D0-D7) pins.
The data will be clocked into the FPGA on the following ris-
ing edge of the CCLK. Neither Express nor SelectMAP uti-
lize a Length Count, so a free-running oscillator may be
used. See Figure 6.
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
or
Parallel
Interface
CEO
D0 DATA
(Serial or Parallel
[Express/SelectMAP] Mode)
7
D[1:7]
Express Mode and
SelectMAP Interface
CF
Figure 1: XQ18V04 Series Block Diagram
DS026_01_021000
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS082 (v1.2) November 5, 2001
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778