X5001 Datasheet, PDF (7/19 Pages) Xicor Inc. – CPU Supervisor

X5001
Table 1. Instruction Set Definition
Instruction Format
Instruction Name and Operation
0000 0110
EWDC: Enable Watchdog Change Operation
0000 0100
DWDC: Disable Watchdog Change Operation
0000 0001
SWDT: Set Watchdog Timer control bits:
Instruction followed by contents of register: 000(WD₁) (WD₀)000
See Watchdog Timer Settings and Figure 3.
0000 0101
RWDT: Read Watchdog Timer control bits
Notes: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
Figure 1. Read Watchdog Timer setting
CS
SCK
SI
01234567
RWDT
INSTRUCTION
WW
SO
DD
10
Figure 2. Enable Watchdog Change/Disable Watchdog Change Sequence
CS
SCK
SI
01234567
INSTRUCTION
(1 BYTE)
HIGH IMPEDANCE
SO
7038 FRM T03
...
...
...
7