X5001 Datasheet, PDF (6/19 Pages) Xicor Inc. – CPU Supervisor

X5001
spi Interface
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families.
The device monitors the CS/WDI line and asserts RESET
output if there is no activity within user selctable time-out
period. The device also monitors the Vcc supply and
asserts the RESET if Vcc falls below a preset minimum
(V_TRIP). The device contains an 8-bit Watchdog Timer
Register to control the watchdog time-out period. The cur-
rent settings are accessed via the SI and SO pins.
All instructions (Table 1) and data are transferred MSB
first. Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Watchdog Timer Register
7
6543210
0
0
0 WD₁ WD₀ 0
0
0
Watchdog Timer Control Bits
The Watchdog Timer Control bits, WD₀ and WD₁, select
the Watchdog Time-out Period. These nonvolatile bits are
programmed with the Set Watchdog Timer (SWDT)
instruction.
Watchdog Control Bits
WD1
WD0
0
0
0
1
1
0
1
1
Watchdog Time-out
(Typical)
1.4 Seconds
600 Milliseconds
200 Milliseconds
Disabled
Write Watchdog Register Operation
Changing the Watchdog Timer Register is a two step pro-
cess. First, the change must be enabled with by setting
the Watchdog Change Latch (see below). This instruction
is followed by the Set Watchdog Timer (SWDT) instruc-
tion, which includes the data to be written (Figure 5). Data
bits 3 and 4 contain the Watchdog settings and data bits
0, 1, 2, 5, 6 and 7 must be “0” .
Watchdog Change Latch
The Watchdog Change Latch must be SET before a Write
Watchdog Timer Operation is initiated. The Enable
Watchdog Change (EWDC) instruction will set the latch
and the Disable Watchdog Change (DWDC) instruction
will reset the latch (See Figure 2.) This latch is automati-
cally reset upon a power-up condition and after the com-
pletion of a valid nonvolatile write cycle.
Read Watchdog Timer Register Operation
If there is not a nonvolatile write in progress, the Read
Watchdog Timer instruction returns the setting of the
watchdog timer control bits. The other bits are reserved
and will return ’0’ when read. See Figure 3.
If a nonvolatile write is in progress, the Read Watchdog
Timer Register Instruction returns a HIGH on SO. When
the nonvolatile write cycle is completed, a seperate Read
Watchdog Timer instruction should be used to determine
the current status of the Watchdog control bits.
RESET Operation
The RESET (X5001) output is designed to go LOW
whenever V_CC has dropped below the minimum trip point
and/or the Watchdog timer has reached its programmable
time-out limit.
The RESET output is an open drain output and requires a
pull up resistor.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The Watchdog Change Latch is reset.
• The RESET Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent inad-
vertent writes:
• A EWDC instruction must be issued to enable a change
to the watchdog timeout setting.
• CS must come HIGH at the proper clock count in order
to implement the requested changes to the watchdog
timeout setting.
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