X5001 Datasheet, PDF (11/19 Pages) Xicor Inc. – CPU Supervisor

X5001
Figure 1. Data Output Timing
CS
SCK
SO
t _CYC
t_V
MSB OUT
t_HO
MSB–1 OUT
t_WH
t _WL
t _LAG
t_DIS
LSB OUT
SI
ADDR
LSB IN
Figure 2. Data Input Timing
CS
SCK
SI
t_LEAD
t_SU
t_H
MSB IN
SO
HIGH IMPEDANCE
t_CS
t_LAG
t_RI
t _FI
LSB IN
Figure 1. Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
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