X5001 Datasheet, PDF (10/19 Pages) Xicor Inc. – CPU Supervisor

X5001
Figure 1. EQUIVALENT A.C. LOAD CIRCUIT
3V
5V
1.64KΩ
OUTPUT
1.64KΩ
100pF
3.3KΩ
RESET
30pF
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
f_SCK
t_CYC
t_LEAD
t_LAG
t_WH
t_WL
t_SU
t_H
t_RI⁽³⁾
t_FI⁽³⁾
t_CS
t_WC⁽⁴⁾
Parameter
Clock Frequency
Cycle Time
CS Lead Time
CS Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
1.8V–3.6V
Min.
Max.
0
1
1000
400
400
400
400
100
100
2
2
250
10
2.7V–5.5V
Min.
Max.
0
2
500
200
200
200
200
50
50
2
2
150
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ms
Data Output Timing
Symbol
f_SCK
t_DIS
t_V
t_HO
t_RO⁽³⁾
t_FO⁽³⁾
Parameter
Clock Frequency
Output Disable Time
Output Valid from Clock Low
Output Hold Time
Output Rise Time
Output Fall Time
1.8V–3.6V
Min.
Max.
0
1
400
400
0
300
300
2.7V–5.5V
Min.
Max.
0
2
200
200
0
150
150
Units
MHz
ns
ns
ns
ns
ns
Notes:
(3) This parameter is periodically sampled and not 100% tested.
(4) t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
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