W25B40 Datasheet, PDF (9/36 Pages) Winbond – 4M-BIT SERIAL FLASH MEMORY WITH BOOT AND PARAMETER SECTORS

W25B40/W25B40A
7. FUNCTIONAL DESCRIPTION
7.1 SPI OPERATIONS
7.1.1 SPI Modes
The W25B40 / W25B40A is accessed through an SPI compatible bus consisting of four signals: Serial
Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus
operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode
3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the
CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
7.1.2 Hold Function
The /HOLD signal allows the W25B40 / W25B40A operation to be paused while it is actively selected
(when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals
are shared with other devices. For example, consider if the page buffer was only partially written when
a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of
the instruction and the data in the buffer so programming can resume where it left off once the bus is
available again.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the
full duration of the /HOLD operation to avoid resetting the internal logic state of the device.
7.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the
W25B40 / W25B40A provides several means to protect data from inadvertent writes.
7.2.1 Write Protect Features
• Device resets when VCC is below threshold.
• Time delay write disable after Power-up.
• Write enable/disable instructions.
• Automatic write disable after program and erase.
• Software write protection using Status Register.
• Hardware write protection using Status Register and /WP pin.
Publication Release Date: January 6, 2006
-9-
Revision M