W25B40 Datasheet, PDF (6/36 Pages) Winbond – 4M-BIT SERIAL FLASH MEMORY WITH BOOT AND PARAMETER SECTORS

W25B40/W25B40A
4.3 Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
4.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP2, BP1 and BP0) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is
active low.
4.5 Hold (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought
low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function
can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)
4.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI "Operations")
4.7 Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially
written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input
pin.
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