W25B40 Datasheet, PDF (11/36 Pages) Winbond – 4M-BIT SERIAL FLASH MEMORY WITH BOOT AND PARAMETER SECTORS

W25B40/W25B40A
write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Chip Erase and Write Status Register.
8.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array
can be protected from Program and Erase instructions (see Status Register Memory Protection table).
The factory default setting for the Block Protection Bits is 0, none of the array protected. The Block
Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write
Protect (/WP) pin is low.
8.1.4 Reserved Bits
Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0 for these
bit locations. It is recommended to mask out the reserved bit when testing the Status Register. Doing
this will ensure compatibility with future devices.
8.1.5 Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a non-volatile read/write bit in the status register (S7) that can
be used in conjunction with the Write Protect (/WP) pin to disable writes to the status register. When
the SRP bit is set to a 0 state (factory default) the /WP pin has no control over the status register.
When the SRP pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is
low. When the /WP pin is high the Write Status Register instruction is allowed.
Figure 3. Status Register Bit Locations
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Publication Release Date: January 6, 2006
Revision M