W25B40 Datasheet, PDF (12/36 Pages) Winbond – 4M-BIT SERIAL FLASH MEMORY WITH BOOT AND PARAMETER SECTORS

W25B40/W25B40A
8.1.6 Write Protection Operation - Bottom Boot Sector Organization
STATUS REGISTER
BP2 BP1 BP0
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
W25B40 / W25B40A (4M-BIT) MEMORY PROTECTION
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
ALL
000000h - 07FFFFh
512KB
ALL
0 thru 7
000000h - 03FFFFh
256KB
Lower 1/2
0 thru 4
000000h - 00FFFFh
64KB
Lower 1/8
0 thru 3
000000h - 007FFFh
32KB
Lower 1/16
0 thru 2
000000h - 003FFFh
16KB
Lower 1/32
0 thru 1
000000h - 001FFFh
8KB
Lower 1/64
0
000000h - 000FFFh
4KB
Lower 1/128
NONE
NONE
NONE
NONE
8.1.7 Write Protection Operation - Top Boot Sector Organization (Special Order)
STATUS REGISTER
BP2 BP1 BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
W25B40 / W25B40A (4M-BIT) MEMORY PROTECTION
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
NONE
NONE
NONE
NONE
11
07F000h - 07FFFFh
4KB
Upper 1/128
10 thru 11 07E000h - 07FFFFh
8KB
Upper 1/64
9 thru 11
07C000h - 07FFFFh
16KB
Upper 1/32
8 thru 11
078000h - 07FFFFh
32KB
Upper 1/16
7 thru 11
070000h - 07FFFFh
64KB
Upper 1/8
4 thru 11
040000h - 07FFFFh
256KB
Upper 1/2
ALL
000000h - 07FFFFh
512KB
ALL
8.2 INSTRUCTIONS
The instruction set of the W25B40 / W25B40A consists of twelve basic instructions that are fully
controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 17. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (/CS) driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
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