W83977EF Datasheet, PDF (87/150 Pages) Winbond – WINBOND I/O

W83977EF
7.2.2 Watch Dog Timer Output
Watch Dog Timer contains a one second/minute resolution down counter, CRF2 of Logical Device 8,
and two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down
counter can be programmed within the range from 1 to 255 seconds/minutes. Writing any new non-
zero value to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also
contains non-zero value) will cause the Watch Dog Timer to reload and start to count down from the
new value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of
WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable
in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is
enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1.
7.2.3 Power LED
The Power LED function provides 1~1/8 Hertz rate toggle pulse output with 50 percent duty cycle.
Table 7.2.2 shows how to enable Power LED.
Table 7.2.2
WDT_CTRL1 BIT[1]
1
0
0
0
WDT_CTRL0 BIT[3]
X
0
1
1
WDT_CTRL1 BIT[0]
X
X
0
1
POWER LED STATE
Toggle pulse
Continuous high or low *
Continuous high or low *
Toggle pulse
* Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configuration registers.
7.2.4 General Purpose Address Decoder
General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The
address base is stored at CR62, CR63, CR64, and CR65 of logical device 7 for GP14 and GP15. The
decoding range can be programmed to 1~8 byte boundary. The decoding output is normally active
low. Users can alter its polarity through the polarity bit of the GP14 and GP15 configuration register.
Publication Release Date: April 2003
-81 -
Revision 1.1