W83977EF Datasheet, PDF (122/150 Pages) Winbond – WINBOND I/O

W83977EF
Bit 0: GP10IRQEN.
IRQ.
= 0 disable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's
IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's
CRF9 (Default 0x00)
Bit 7 - 3: Reserved. Return zero when read.
Bit 2: SCI_EN: Select the power management events to be either an SCI# OR SMII# interrupt for
the IRQ events. Note that: this bit is valid only when SMISCI_OE = 1.
= 0 the power management events will generate an SMI# event.
= 1 the power management events will generate an SCI# event.
Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices
= 0 1 second.
= 1 8 milli-seconds.
Bit 0: SMISCI_OE: This is the SMI# and SCI# enable bit.
= 0 neither SMI# nor SCI# will be generated. Only the IRQ status bit is set.
= 1 an SMI# or SCI# event will be generated.
CRFE, FF (Default 0x00)
Reserved for Winbond test.
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Publication Release Date: April 2003
Revision 1.1