W83977EF Datasheet, PDF (4/150 Pages) Winbond – WINBOND I/O

W83977EF
3.2.4 Handshake Status Register (HSR) (Read/Write) ................................................................. 49
3.2.5 UART FIFO Control Register (UFR) (Write only).................................................................. 50
3.2.6 Interrupt Status Register (ISR) (Read only).......................................................................... 51
3.2.7 Interrupt Control Register (ICR) (Read/Write) ...................................................................... 52
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) .................................................... 52
3.2.9 User-defined Register (UDR) (Read/Write) .......................................................................... 52
4.0 INFRARED (IR) PORTS ................................................................................................................. 54
4.1 IR PORT ...................................................................................................................................... 54
5.0 PARALLEL PORT ......................................................................................................................... 55
5.1 PRINTER INTERFACE LOGIC ............................................................................................................ 55
5.2 ENHANCED PARALLEL PORT (EPP)................................................................................................. 56
5.2.1 Data Swapper ................................................................................................................. 56
5.2.2 Printer Status Buffer ........................................................................................................ 57
5.2.3 Printer Control Latch and Printer Control Swapper ........................................................ 58
5.2.4 EPP Address Port............................................................................................................ 58
5.2.5 EPP Data Port 0-3 ........................................................................................................... 59
5.2.6 Bit Map of Parallel Port and EPP Registers .................................................................... 59
5.2.7 EPP Pin Descriptions...................................................................................................... 60
5.2.8 EPP Operation................................................................................................................. 60
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT ........................................................................... 61
5.3.1 ECP Register and Mode Definitions ................................................................................ 61
5.3.2 Data and ecpAFifo Port ................................................................................................... 62
5.3.3 Device Status Register (DSR) ........................................................................................ 62
5.3.4 Device Control Register (DCR) ....................................................................................... 63
5.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010................................................................. 64
5.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011...................................................................... 64
5.3.7 TFIFO (Test FIFO Mode) Mode = 110 ............................................................................ 64
5.3.8 CNFGA (Configuration Register A) Mode = 111 ............................................................. 64
5.3.9 CNFGB (Configuration Register B) Mode = 111 ............................................................. 64
5.3.10 ECR (Extended Control Register) Mode = all ................................................................. 65
5.3.11 Bit Map of ECP Port Registers ........................................................................................ 66
5.3.12 ECP Pin Descriptions ...................................................................................................... 67
5.3.13 ECP Operation................................................................................................................. 68
5.3.14 FIFO Operation................................................................................................................ 68
5.3.15 DMA Transfers................................................................................................................. 69
5.3.16 Programmed I/O (NON-DMA) Mode ............................................................................... 69
5.4 EXTENSION FDD MODE (EXTFDD) .......................................................................................... 69
5.5 EXTENSION 2FDD MODE (EXT2FDD) ...................................................................................... 69
6. KEYBOARD CONTROLLER..................................................................................................... 70
6.1 OUTPUT BUFFER........................................................................................................................... 70
6.2 INPUT BUFFER .............................................................................................................................. 70
6.3 STATUS REGISTER ........................................................................................................................ 71
6.4 COMMANDS............................................................................................................................... 72
6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC........................................................... 73
6.5.1 KB Control Register (Logic Device 5, CR-F0) ................................................................. 74
6.5.2 Port 92 Control Register (Default Value = 0x24)............................................................. 74
6.6 ONNOW / SECURITY KEYBOARD AND MOUSE WAKE-UP.............................................................. 75
Publication Release Date: April 2003
-III -
Revision 1.1