W83977EF Datasheet, PDF (115/150 Pages) Winbond – WINBOND I/O

W83977EF
Bit 2: Mouse interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Mouse interrupt
= 0 Watch Dog Timer is not affected by Mouse interrupt
Bit 1: Keyboard interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Keyboard interrupt
= 0 Watch Dog Timer is not affected by Keyboard interrupt
Bit 0: Reserved.
CRF4 (WDT_CTRL1, Default 0x00)
Watch Dog Timer Control Register #1
Bit 7: Reserved
Bit 6:
= 1 Watch Dog counter counts in seconds.
= 0 Watch Dog counter counts in minutes.
Bit 5-4: Power LED toggle pulse frequency select
= 00 Power LED toggle pulse frequency is 1Hz
= 01 Power LED toggle pulse frequency is 1/2Hz
= 10 Power LED toggle pulse frequency is 1/4Hz
= 11 Power LED toggle pulse frequency is 1/8Hz
Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
= 1 Enable
= 0 Disable
Bit 2: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.
Bit 1: Enable Power LED toggle pulse with 50% duty cycle , R/W
= 1 Enable
= 0 Disable
Bit 0: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred.
= 0 Watch Dog Timer counting
*Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and
then
connect to set the Bit 0(Watch Dog Timer Status). The ORed signal is self-clearing.
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Publication Release Date: April 2003
Revision 1.1