W83977EF Datasheet, PDF (117/150 Pages) Winbond – WINBOND I/O

W83977EF
CRE3 (Read only) Keyboard/Mouse Wake-Up Status Register
Bit 7-4: Reserved.
Bit 4: POWERRESUME_STS. The bit is set after powerloss occured and cleared by
reading this register.
Bit 3: Revered
Bit 2: PANSW_STS. The Panel switch event is caused by PANSWIN#. This bit is cleared by
reading this register.
Bit 1: Mouse_STS. The Panel switch event is caused by Mouse Wake-Up event. This bit is
cleared by reading this register.
Bit 0: Keyboard_STS. The Panel switch event is caused by Keyboard Wake-Up event. This bit is
cleared by reading this register.
CRE4 OnNow/Powerloss Control Register.
Bit 7: Powerloss Control bit 2.
Bit 6: Powerloss Control bit 1.
Bit 5: Powerloss Control bit 0.
Bit 4: 32KHz clock source select.
Bit 3: Reserved.
Bit 2: Reserved.
Bit 1-0: Reserved.
CRE5 (Default 0x00)
Bit 7: Reserved.
Bit 6 - 0: Compared Code Length. When the compared codes are storaged in the data register,
these data length should be written to this register.
CRE6 (Default 0x00)
Bit 7 - 0: Reserved.
-111 -
Publication Release Date: April 2003
Revision 1.1