W83977EF Datasheet, PDF (58/150 Pages) Winbond – WINBOND I/O

W83977EF
0 0 1 0 Third
TBR Empty
TBR empty
0 0 0 0 Fourth Handshake status
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
1. Write data into TBR
2. Read ISR (if priority is
third)
Read HSR
3.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
7 65 4 3 2 1 0
0 0 00
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud ge₁n₆erator that uses 24 MHz to
generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table in the next page illustrates the use of the baud generator with a frequency of
1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud
generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed
mode, the data transmission rate can be as high as 1.5M bps.
3.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
TABLE 3-5 BAUD RATE TABLE
Pre-Div: 13
1.8461M Hz
BAUD RATE FROM DIFFERENT PRE-DIVIDER
Pre-Div:1.625 Pre-Div: 1.0
14.769M Hz
24M Hz
Decimal divisor used
to generate 16X
clock
Error Percentage between
desired and actual
Publication Release Date: April 2003
-52 -
Revision 1.1