W83977EF Datasheet, PDF (52/150 Pages) Winbond – WINBOND I/O

W83977EF
+0
BDLAB = 0
Receiver
Buffer
Register
(Read Only)
+0
Transmitter
BDLAB = 0 ^{Buffer Register}
(Write Only)
+1
Interrupt Control
BDLAB = 0
Register
RBR
TBR
ICR
+2
Interrupt Status ISR
Register
(Read Only)
RX Data
Bit 0
TX Data
Bit 0
RBR Data
Ready
Interrupt
Enable
(ERDRI)
"0" if
Interrupt
Pending
RX Data
Bit 1
TX Data
Bit 1
TBR
Empty
Interrupt
Enable
(ETBREI)
Interrupt
Status
Bit (0)
RX Data
Bit 2
TX Data
Bit 2
USR
Interrupt
Enable
(EUSRI)
Interrupt
Status
Bit (1)
RX Data
Bit 3
TX Data
Bit 3
HSR
Interrupt
Enable
(EHSRI)
Interrupt
Status
Bit (2)**
RX Data
Bit 4
TX Data
Bit 4
0
0
RX Data
Bit 5
TX Data
Bit 5
0
0
+2
UART FIFO UFR
FIFO
RCVR
XMIT
DMA
Reserved Reversed
Control
Enable
FIFO
FIFO
Mode
Register
Reset
Reset
Select
(Write Only)
+3
UART Control UCR
Data
Data
Multiple
Parity
Even
Parity
Register
Length
Length
Stop Bits
Bit
Parity
Bit Fixed
Select
Select
Enable
Enable
Enable
Enable
Bit 0
(DLS0)
Bit 1
(DLS1)
(MSBE)
(PBE)
(EPE)
PBFE)
+4
Handshake HCR
Data
Request Loopback
IRQ
Internal
0
Control
Terminal
to
RI
Enable Loopback
Register
Ready
Send
Input
Enable
(DTR)
(RTS)
+5
UART Status USR RBR Data Overrun Parity Bit No Stop
Silent
TBR
Register
Ready
Error
Error
Bit
Byte
Empty
(RDR)
(OER)
(PBER)
Error
(NSER)
Detected
(SBD)
(TBRE)
+6
Handshake HSR
CTS
DSR
RI Falling
DCD
Clear
Data Set
Status Register
Toggling Toggling
Edge
Toggling
to Send
Ready
(TCTS)
(TDSR)
(FERI)
(TDCD)
(CTS)
(DSR)
+7
User Defined UDR
Bit 0
Register
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
+0
Baudrate
BLL
BDLAB = 1 ^{Divisor Latch}
Low
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
+1
Baudrate
BHL
BDLAB = 1 ^{Divisor Latch}
High
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
RX Data
Bit 6
RX Data
Bit 7
TX Data
Bit 6
0
TX Data
Bit 7
0
FIFOs
FIFOs
Enabled Enabled
**
**
RX
RX
Interrupt Interrupt
Active Level Active Level
(LSB)
(MSB)
Set
Silence
Enable
(SSE)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
0
0
TSR
Empty
(TSRE)
Ring
Indicator
(RI)
Bit 6
RX FIFO
Error
Indication
(RFEI) **
Data Carrier
Detect
(DCD)
Bit 7
Bit 6
Bit 7
Bit 14
Bit 15
Publication Release Date: April 2003
-46 -
Revision 1.1