W25Q32FWZPIG-TR Datasheet, PDF (80/94 Pages) Winbond – 1.8V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q32FW
AC Electrical Characteristics (cont’d)
DESCRIPTION
/HOLD Active Hold Time relative to CLK
SYMBOL ALT
MIN
tCHHH
5
SPEC
TYP
MAX
UNIT
ns
/HOLD Not Active Setup Time relative to CLK
tHHCH
5
ns
/HOLD Not Active Hold Time relative to CLK
tCHHL
5
ns
/HOLD to Output Low-Z
tHHQX⁽²⁾
tLZ
7
ns
/HOLD to Output High-Z
tHLQZ⁽²⁾
tHZ
12
ns
Write Protect Setup Time Before /CS Low
tWHSL⁽³⁾
20
ns
Write Protect Hold Time After /CS High
tSHWL⁽³⁾
100
ns
/CS High to Power-down Mode
/CS High to Standby Mode without ID Read
/CS High to Standby Mode with ID Read
tDP⁽²⁾
tRES1⁽²⁾
tRES2⁽²⁾
3
µs
3
µs
1.8
µs
/CS High to next Instruction after Suspend
tSUS⁽²⁾
20
µs
/CS High to next Instruction after Reset
tRST⁽²⁾
30
µs
/RESET pin Low period to reset the device
tRESET⁽²⁾
1⁽⁵⁾
µs
Write Status Register Time
tW
10
25
ms
Byte Program Time (First Byte) ⁽⁴⁾
tBP1
30
60
µs
Additional Byte Program Time (After First Byte) ⁽⁴⁾
tBP2
2.5
12
µs
Page Program Time
tPP
0.7
5
ms
Sector Erase Time (4KB)
tSE
100
400
ms
Block Erase Time (32KB)
tBE1
250
1,600
ms
Block Erase Time (64KB)
tBE2
350
2,000
ms
Chip Erase Time
tCE
20
50
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes
programmed.
5. It is possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure reliable operation.
6. Tested on sample basis and specified through design and characterization data. TA = 25°C, VCC = 1.8V, 25% driver strength.4-bytes address
alignment for QPI/SPI Quad Read
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