W25Q32FWZPIG-TR Datasheet, PDF (74/94 Pages) Winbond – 1.8V 32M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q32FW
8.2.41 Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the W25Q32FW provide a software
Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going
internal operations will be terminated and the device will return to its default power-on state and lose all the
current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status,
Program/Erase Suspend status, Read parameter setting (P7-P0), and Wrap Bit setting (W6-W4).
“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To
avoid accidental reset, both instructions must be issued in sequence. Any other commands other than
“Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new
sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset
command is accepted by the device, the device will take approximately tRST=30us to reset. During this
period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the
SUS bit in Status Register before issuing the Reset command sequence.
/CS
CLK
Mode 3
Mode 0
DI
(IO₀)
DO
(IO₁)
01234567
Instruction (66h)
Mode 3
Mode 0
012345
Instruction (99h)
67
Mode 3
Mode 0
High Impedance
Figure 56a. Enable Reset and Reset Instruction Sequence (SPI Mode)
/CS
CLK
IO₀
Mode 3
Mode 0
01
Instruction
66h
Mode 3
Mode 0
01
Instruction
99h
Mode 3
Mode 0
IO₁
IO₂
IO₃
Figure 56b. Enable Reset and Reset Instruction Sequence (QPI Mode)
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