W9425G8EH Datasheet, PDF (8/53 Pages) Winbond – 8M × 4 BANKS × 8 BITS DDR SDRAM

6. BLOCK DIAGRAM
W9425G8EH
CLK
CLK
CKE
DLL
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
A0
A9
A11
A12
BS0
BS1
ADDRESS
BUFFER
MODE
REGISTER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
PREFETCH REGISTER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE: The cell array configuration is 8192 * 1024 * 8
DQ0
DQ7
DQS
DM
Publication Release Date: Jul. 04, 2008
-8-
Revision A01