W9425G8EH Datasheet, PDF (16/53 Pages) Winbond – 8M × 4 BANKS × 8 BITS DDR SDRAM

W9425G8EH
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6
A5
A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CAS LATENCY
Reserved
Reserved
2
3
Reserved
Reserved
2.5
Reserved
7.10.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.
7.10.5 Mode Register /Extended Mode register change bits (BS0, BS1)
These bits are used to select MRS/EMRS.
BS1
BS0
0
0
0
1
1
x
A12-A0
Regular MRS Cycle
Extended MRS Cycle
Reserved
7.10.6 Extended Mode Register field
1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0
0
1
DLL
Enable
Disable
2) Output Driver Size Control field (A1)
This bit is used to select Output Driver Size, both Full strength and Half strength are based on
JEDEC standard.
A1
OUTPUT DRIVER
0
Full Strength
1
Half Strength
7.10.7 Reserved field
• Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to "0" for normal operation.
• Reserved bits (A9, A10, A11, A12)
These bits are reserved for future operations. They must be set to "0" for normal operation.
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Publication Release Date: Jul. 04, 2008
Revision A01