W9425G8EH Datasheet, PDF (25/53 Pages) Winbond – 8M × 4 BANKS × 8 BITS DDR SDRAM

W9425G8EH
9.5 DC Characteristics
SYM.
PARAMETER
IDD0
IDD1
IDD2P
IDD2F
IDD2N
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Operating current: One Bank Active-Precharge; tRC = tRC min; tCK
= tCK min; DQ, DM and DQS inputs changing twice per clock
cycle; Address and control inputs changing once per clock cycle
Operating current: One Bank Active-Read-Precharge; Burst = 2;
tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and
control inputs changing once per clock cycle.
Precharge Power Down standby current: All Banks Idle; Power
down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ,
DQS and DM
Idle floating standby current: CS > VIH min; All Banks Idle; CKE
> VIH min; Address and other control inputs changing once per
clock cycle; Vin = VREF for DQ, DQS and DM
Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH
min; tCK = tCK min; Address and other control inputs changing
once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS
and DM
Idle quiet standby current: CS > VIH min; All Banks Idle; CKE >
VIH min; tCK = tCK min; Address and other control inputs stable;
Vin > VREF for DQ, DQS and DM
Active Power Down standby current: One Bank Active; Power
down mode; CKE < VIL max; tCK = tCK min
Active standby current: CS > VIH min; CKE > VIH min; One Bank
Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and
DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
Operating current: Burst = 2; Reads; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle;
CL=3; tCK = tCK min; IOUT = 0mA
Operating current: Burst = 2; Write; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle;
CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per
clock cycle
Auto Refresh current: tRC = tRFC min
Self Refresh current: CKE < 0.2V
Random Read current: 4 Banks Active Read with activate every
20nS, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT
= 0mA; DQ, DM and DQS inputs changing twice per clock cycle;
Address changing once per clock cycle
MAX.
-5 -6 -75
110 110 110
150 150 150
20
20
20
45
45
40
45
45
40
40
40
35
20
20
20
70
70
65
180 170 160
180 170 160
190 190 190
3
3
3
300 300 300
UNIT NOTES
7
7, 9
7
7
7
mA
7
7, 9
7
7
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Publication Release Date: Jul. 04, 2008
Revision A01